Digital VLSI Testing Course | IIT Kharagpur | Prof. Santanu Chattopadhyay
Course Details
| Exam Registration | 1370 |
|---|---|
| Course Status | Ongoing |
| Course Type | Core |
| Language | English |
| Duration | 12 weeks |
| Categories | Electrical, Electronics and Communications Engineering |
| Credit Points | 3 |
| Level | Undergraduate/Postgraduate |
| Start Date | 19 Jan 2026 |
| End Date | 10 Apr 2026 |
| Enrollment Ends | 02 Feb 2026 |
| Exam Registration Ends | 20 Feb 2026 |
| Exam Date | 25 Apr 2026 IST |
| NCrF Level | 4.5 — 8.0 |
Master Digital VLSI Testing with IIT Kharagpur's Expert-Led Course
In the rapidly evolving world of semiconductor design, creating a complex chip is only half the battle. Ensuring it works flawlessly is the other, often more challenging, half. Digital VLSI Testing is the critical discipline that bridges this gap, and it now occupies a staggering 60-80% of the entire VLSI design cycle. For aspiring and practicing engineers, mastering these principles is no longer optional—it's essential.
We are excited to present a detailed overview of a premier educational offering: a comprehensive 12-week course on Digital VLSI Testing, instructed by the renowned Prof. Santanu Chattopadhyay from IIT Kharagpur. This course is meticulously designed to equip you with the foundational and advanced knowledge required to tackle modern testing challenges.
Meet Your Instructor: Prof. Santanu Chattopadhyay
Learning from an expert with both deep academic knowledge and extensive research experience is invaluable. Prof. Chattopadhyay brings precisely that to this course.
- Academic Credentials: BE (Computer Science, Calcutta University), M.Tech & PhD (Computer Science, IIT Kharagpur).
- Current Role: Professor, Department of Electronics and Electrical Communication Engineering, IIT Kharagpur.
- Rich Experience: Previously served as faculty at IIEST Shibpur and IIT Guwahati.
- Research Expertise: Digital Design, Embedded Systems, SoC/NoC Design & Test, Power- and Thermal-aware VLSI Testing.
- Proven Track Record: Authored over 150 publications and several textbooks. A Senior Member of IEEE and Associate Editor for IET Journals.
Who Should Take This Course?
This course is crafted to be accessible yet profoundly insightful for a wide audience.
- Intended Audience: Undergraduate & Postgraduate students, VLSI design engineers, testing professionals, and any learner interested in semiconductor technology.
- Prerequisites: A fundamental understanding of Digital Design or Digital Logic is required to fully grasp the concepts.
- Industry Support: This curriculum is highly relevant and recognized by companies involved in VLSI chip development worldwide.
Course Overview: What You Will Learn
Structured over 12 intensive weeks, the course progresses from core principles to specialized advanced topics. Here’s a breakdown of the curriculum:
| Week | Core Topics Covered |
|---|---|
| Week 1-2 | Introduction & DFT Basics: Fault models, testability analysis, scan architecture. |
| Week 3-4 | Fault Simulation: Logic simulation, fault simulation techniques. |
| Week 5-6 | Test Generation: Boolean difference, ATPG algorithms, BIST introduction. |
| Week 7-8 | BIST & Compression: Logic BIST architectures, test stimulus compression. |
| Week 9-10 | Advanced Compression & Memory Test: Response compression, RAM fault models. |
| Week 11-12 | Memory BIST & Power/Thermal Issues: Low-power ATPG, thermal-aware testing techniques. |
Why is Digital VLSI Testing So Crucial?
As integrated circuits contain billions of transistors, the probability of a manufacturing defect or a design flaw slipping through increases exponentially. A single faulty chip in a critical system can have catastrophic consequences. This course addresses the heart of this challenge:
- Ensuring Yield & Quality: Learn structured methodologies to detect faulty chips after manufacturing, ensuring high product yield and reliability.
- Mastering Design for Testability (DFT): DFT is now a mature, non-negotiable part of the design flow. This course provides a solid foundation in scan design, BIST, and test compression—the pillars of modern DFT.
- Solving Modern Challenges: Tackle advanced issues like power dissipation during test and thermal management, which are critical for today's dense, high-performance chips.
Enroll and Transform Your VLSI Career
Whether you are a student aiming to enter the semiconductor industry or a professional seeking to solidify your testing expertise, this Digital VLSI Testing course offers a world-class learning opportunity. Under the guidance of Prof. Santanu Chattopadhyay, you will gain the practical and theoretical knowledge to design better quality, more manufacturable VLSI products.
Take the next step in mastering the art and science of VLSI verification. Equip yourself with the skills that define the backbone of reliable electronics design and open doors to cutting-edge careers in semiconductor companies globally.
Enroll Now →