VLSI Physical Design Course | Prof. Indranil Sengupta IIT Kharag | 12-Week Program
Course Details
| Exam Registration | 904 |
|---|---|
| Course Status | Ongoing |
| Course Type | Elective |
| Language | English |
| Duration | 12 weeks |
| Categories | Computer Science and Engineering, VLSI design |
| Credit Points | 3 |
| Level | Undergraduate/Postgraduate |
| Start Date | 19 Jan 2026 |
| End Date | 10 Apr 2026 |
| Enrollment Ends | 02 Feb 2026 |
| Exam Registration Ends | 20 Feb 2026 |
| Exam Date | 25 Apr 2026 IST |
| NCrF Level | 4.5 — 8.0 |
Master the Art of VLSI Physical Design with an Expert from IIT Kharagpur
The world of modern electronics is built upon the foundation of Very-Large-Scale Integration (VLSI). While conceptualizing a chip is one challenge, transforming that logic into an efficient, manufacturable, and high-performance physical layout is another critical discipline. This is where VLSI Physical Design comes in—the bridge between circuit design and silicon reality.
We are excited to present a comprehensive, 12-week course on VLSI Physical Design, meticulously crafted and delivered by one of India's foremost authorities in the field, Prof. Indranil Sengupta from IIT Kharagpur. This course is designed to equip students and professionals with the foundational knowledge and algorithmic understanding essential for a career in semiconductor design.
About the Instructor: Prof. Indranil Sengupta
Learning from an experienced academician and researcher is invaluable. Prof. Indranil Sengupta brings over 28 years of teaching and research experience at IIT Kharagpur's Department of Computer Science and Engineering, where he is a full Professor and former Head of Department.
His credentials are exemplary:
- Education: B.Tech., M.Tech., and Ph.D. in Computer Science and Engineering from the University of Calcutta.
- Research Expertise: Cryptography & Network Security, VLSI Design & Testing, and Mobile Computing.
- Academic Leadership: Guided 22 PhD students and authored over 200 publications.
- Professional Recognition: A Senior Member of IEEE and General Chair for prestigious international conferences including Asian Test Symposium (ATS) and International Symposium on VLSI Design and Test (VDAT).
His deep industry and academic insights ensure the course content is both theoretically sound and practically relevant.
Course Overview: What You Will Learn
This undergraduate/postgraduate level course provides a structured journey through the entire VLSI physical design automation flow. It is intended for students of Computer Science, Electronics & Communication, and Electrical Engineering.
Prerequisites: A basic understanding of digital circuit design is recommended.
Industry Support: The curriculum is highly valued by leading semiconductor and EDA companies, including Intel, Cadence, Mentor Graphics, Synopsys, and Xilinx.
Detailed 12-Week Course Layout
The course is systematically divided into weekly modules, each building upon the last to provide a holistic understanding.
| Week | Core Topics Covered |
|---|---|
| Week 1 | Introduction to Physical Design Automation |
| Week 2 | Partitioning, Floorplanning, and Placement |
| Week 3 | Grid Routing and Global Routing |
| Week 4 | Detailed Routing and Clock Design |
| Week 5 | Clock Routing and Power/Ground Network Design |
| Week 6 | Static Timing Analysis (STA) and Timing Closure |
| Week 7 | Physical Synthesis and Performance-Driven Design Flow |
| Week 8 | Interconnect Modeling and Layout Compaction |
| Week 9 | Introduction to Testing, Fault Modeling, and Simulation |
| Week 10 | Test Pattern Generation, Design-for-Test (DFT), and Built-In Self-Test (BIST) |
| Weeks 11 & 12 | Low Power Design Techniques |
Key Learning Outcomes and Career Benefits
By the end of this course, participants will:
- Grasp the complete VLSI physical design flow, from netlist to GDSII.
- Understand the fundamental algorithms and data structures used in EDA tools for partitioning, placement, and routing.
- Learn critical analysis techniques like Static Timing Analysis (STA) for ensuring design performance.
- Acquire knowledge of Design-for-Testability (DFT) and Low-Power design methodologies, which are crucial in modern chip design.
- Appreciate the practical challenges in achieving timing closure, signal integrity, and power efficiency.
This knowledge forms the core skill set for roles such as Physical Design Engineer, CAD Engineer, and ASIC Design Engineer, making it an essential step for anyone targeting the semiconductor industry.
Who Should Enroll?
This course is perfectly suited for:
- Final-year B.Tech/B.E. students in CSE, ECE, or EE.
- M.Tech/M.S. students specializing in VLSI or Microelectronics.
- Industry professionals looking to solidify their understanding of the physical design flow.
- Researchers and academics entering the VLSI domain.
Embark on this 12-week journey to decode the complexities of turning circuit diagrams into powerful silicon chips. With expert guidance from Prof. Indranil Sengupta, you will gain the confidence and knowledge to navigate the challenging and rewarding field of VLSI Physical Design.
Enroll Now →